A methodology for automated design and implementation of complex analog and digital CMOS integrated circuits applying a genetic algorithm and a CAD tool for multiobjective optimization.

 

Authors
Pereira-Arroyo, Roberto
Format
DoctoralThesis
Status
publishedVersion
Description

Tesis (Doctorado en Ciencias Naturales para el Desarrollo) Instituto Tecnológico de Costa Rica, Escuela de Ingeniería Electrónica, 2014.
This dissertation proposes an automated methodology to design and optimize electronic integrated circuits, something that could be called simulation-driven optimization. The concept of Pareto optimality or the so called Pareto front is introduced as a useful analysis tool in order to explore the design space of such circuits. A genetic algorithm (GA) is employed to automatically detect this front in a process that efficiently finds optimal parameterizations and their corresponding values in an aggregate fitness space. Since the problem at hand is inherently a multi-objective optimization task, many different performance measures of the circuits must be able to be easily defined and computed as fitness functions. The methodology has been validated through measurements of several fabricated test cases, using MOSIS fabrication services for a standard 0.5m CMOS technology.
Instituto Tecnológico de Costa Rica. Escuela de Ingeniería Electrónica.

Publication Year
2014
Language
spa
Topic
Algoritmos genéticos
Circuitos integrados
CMOS
Fuente
RepositorioTEC
Get full text
http://hdl.handle.net/2238/6537
Derechos
openAccess
Licencia