Seven levels triphasic inverter design controlled by a state machine
保存先:
| 著者: | |
|---|---|
| フォーマット: | artículo original |
| 状態: | Versión publicada |
| 出版日付: | 2017 |
| その他の書誌記述: | This article describes the design of a seven levels triphasic inverter circuit, separated in three stages: monophasic signal generation stage, control stage and offset stage. For the monophasic signal generation stage was used an asymmetric cascade inverter based thyristors. For the control stage was used a finite state machine with JK flip-flops. For the offset stage, monoestable circuit was preferred over an RC circuit, because it causes significant power losses and negative effects on the output signal. |
| 国: | Portal de Revistas TEC |
| 機関: | Instituto Tecnológico de Costa Rica |
| Repositorio: | Portal de Revistas TEC |
| 言語: | Español |
| OAI Identifier: | oai:ojs.pkp.sfu.ca:article/3200 |
| オンライン･アクセス: | https://revistas.tec.ac.cr/index.php/tec_marcha/article/view/3200 |
| キーワード: | Circuito desfasador circuito inversor electrónica de potencia inversor trifásico máquina de estados puente inversor Inverter bridge inverter circuit offset circuit power electronic state machine triphasic inverter |