Seven levels triphasic inverter design controlled by a state machine
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| 作者: | |
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| 格式: | artículo original |
| 狀態: | Versión publicada |
| Fecha de Publicación: | 2017 |
| 實物特徵: | This article describes the design of a seven levels triphasic inverter circuit, separated in three stages: monophasic signal generation stage, control stage and offset stage. For the monophasic signal generation stage was used an asymmetric cascade inverter based thyristors. For the control stage was used a finite state machine with JK flip-flops. For the offset stage, monoestable circuit was preferred over an RC circuit, because it causes significant power losses and negative effects on the output signal. |
| País: | Portal de Revistas TEC |
| 機構: | Instituto Tecnológico de Costa Rica |
| Repositorio: | Portal de Revistas TEC |
| 語言: | Español |
| OAI Identifier: | oai:ojs.pkp.sfu.ca:article/3200 |
| 在線閱讀: | https://revistas.tec.ac.cr/index.php/tec_marcha/article/view/3200 |
| Palabra clave: | Circuito desfasador circuito inversor electrónica de potencia inversor trifásico máquina de estados puente inversor Inverter bridge inverter circuit offset circuit power electronic state machine triphasic inverter |