Design and implementation of an all-digital timing recovery system for asynchronous communication
保存先:
| 著者: | , |
|---|---|
| フォーマット: | artículo original |
| 状態: | Versión publicada |
| 出版日付: | 2015 |
| その他の書誌記述: | This work addresses the design and implementation of a timing recovery unit for a communication system with parallel reception, 4-PAM modulation, raised cosine filtering and a nominal sampling frequency of 1,1 GHz. The design of the building blocks within the system, as well as simulation results and the physical implementation in FPGA are discussed. |
| 国: | Portal de Revistas TEC |
| 機関: | Instituto Tecnológico de Costa Rica |
| Repositorio: | Portal de Revistas TEC |
| 言語: | Español |
| OAI Identifier: | oai:ojs.pkp.sfu.ca:article/2332 |
| オンライン･アクセス: | https://revistas.tec.ac.cr/index.php/tec_marcha/article/view/2332 |
| キーワード: | 4-PAM modulation communication systems digital signal processing timing recovery. Modulación 4-PAM procesamiento digital de señales recuperación de la temporización sistema de comunicación. |