Design of an MCML gate library using a Genetic Algorithm and Multi-objective Optimization
Wedi'i Gadw mewn:
| Awduron: | , |
|---|---|
| Fformat: | artículo original |
| Statws: | Versión publicada |
| Dyddiad Cyhoeddi: | 2014 |
| Disgrifiad: | In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto front is introduced as a useful analysis tool to explore the design space of each gate that is part of our MCML basic library. A genetic algorithm (GA) is employed to automatically detect this front in a process that efficiently finds optimal parameterizations and their corresponding values in an aggregate fitness space. Measures of the power consumption, propagation delay and output voltage swing are used as fitness functions, since the problem is treated as a multi-objective optimization task. Finally, the results of postlayout simulations, using the AMS 0.35 μm technology are presented. |
| Gwlad: | Portal de Revistas TEC |
| Sefydliad: | Instituto Tecnológico de Costa Rica |
| Repositorio: | Portal de Revistas TEC |
| Iaith: | Español |
| OAI Identifier: | oai:ojs.pkp.sfu.ca:article/2084 |
| Mynediad Ar-lein: | https://revistas.tec.ac.cr/index.php/tec_marcha/article/view/2084 |
| Allweddair: | Algoritmo genético optimización multiobjetivo lógica en modo de corriente automatización del diseño electrónico. Genetic algorithm multi-objective optimization current mode logic electronic design automation. |