An 8-bit TDC implemented with two nested Johnson counters
Tallennettuna:
| Tekijät: | , , , |
|---|---|
| Aineistotyyppi: | artículo original |
| Tila: | Versión publicada |
| Julkaisupäivä: | 2023 |
| Kuvaus: | This work presents a Time-to-Digital Converter implemented using two nested Johnson counters and suitable for time-lapse measurement applications. The proposed structure is composed of two 4-bit nested counters, two digital-logic control networks, two registers and a single decoder. Semi-dynamic logic was used for the decoder to reduce its power consumption. The system has a standard digital output and is powered by a 1.8 V supply with a total power consumption of 32.4 mW. A prototype was fabricated using a TSMC 180 nm CMOS technology. The proposed structure uses a 508 µm x 225 µm area. In addition, this TDC has a standard deviation of 0.78 LSB with a fixed input time interval operating at a frequency of 1 MHz. The proposed structure shows good performance results and repeatability for continuous conversion conditions, these results are attributed to the simplicity of the system and the use of counters with minimum gate delay as the main elements for the TDC. |
| Maa: | Portal de Revistas TEC |
| Organisaatio: | Instituto Tecnológico de Costa Rica |
| Repositorio: | Portal de Revistas TEC |
| Kieli: | Inglés |
| OAI Identifier: | oai:ojs.pkp.sfu.ca:article/6769 |
| Linkit: | https://revistas.tec.ac.cr/index.php/tec_marcha/article/view/6769 |
| Sanahaku: | TDC Jonhson counter semi-dynamic logic nested counters time-lapse measurement time-todigital converter contador Johnson lógica semi-dinámica contadores anidados mediciones de intervalo de tiempo convertidor de tiempo a digital |