Design of a mitigation circuit to improve MOSFET switching in a half-bridge configuration
保存先:
| 著者: | , , |
|---|---|
| フォーマット: | artículo original |
| 状態: | Versión publicada |
| 出版日付: | 2025 |
| その他の書誌記述: | This work addresses the design of a circuit to minimize the adverse effects of MOSFET switching in a half-bridge configuration. MOSFETs suffer from efficiency and stability issues due to parasitic capacitances and inductances. To mitigate these effects, gate-on and gate-off resistors were added, along with a capacitor between the gate and source. These modifications proved effective in simulations and experimental tests, reducing disturbances and voltage spikes while improving system stability. The proposed solution enhances the performance of MOSFETs in high-frequency and high-power applications, increasing energy efficiency and reducing component stress. |
| 国: | Portal de Revistas TEC |
| 機関: | Instituto Tecnológico de Costa Rica |
| Repositorio: | Portal de Revistas TEC |
| 言語: | Español |
| OAI Identifier: | oai:ojs.pkp.sfu.ca:article/7858 |
| オンライン･アクセス: | https://revistas.tec.ac.cr/index.php/tec_marcha/article/view/7858 |
| キーワード: | Commutation Half-bridge Miller inductance MOSFET oscillation Capacitancia de Miller conmutación oscilación medio puente H |